In a conventional method for flow or IC design and manufacturing, a designer (which may be, and usually is, a group of engineers) at the back-end design stage synthesizes a physical layout of circuit patterns and verifies the layouts using various tools. The layout is often called a mask layout, which is a misnomer. The layout actually describes designed and desired or intended patterns on a wafer, and the designer is actually designing wafer patterns for the circuit. The designer typically uses an RC-extraction tool to estimate the resistance and capacitance parameters based on the layout, and runs a circuit simulator based on the RC (transistor characteristics, resistance and capacitance, even including inductance) parameters to verify the functionality of the designed IC. Upon verification, the designer “tapes-out” the layout of wafer patterns to a process group, or a “fab” (that is, a semiconductor fabrication facility), in the same company, affiliate company, or an independent foundry. The fab or process group then has to create a set of masks corresponding to the layout of wafer patterns, before using the masks in photolithography machines to produce the wafer patterns. Patterns on mask are often quite dissimilar to the wafer patterns in order to fabricate semiconductor chips consisting of sub-wavelength features.
These conventional design methods and workflows are becoming increasingly inconvenient, and sometimes non-functional, as a result of requiring increasingly more complicated optical proximity correction (OPC) to the masks and other resolution enhancement techniques (RETs), in order to fabricate deep-sub-wavelength wafer patterns. The difficulty has two aspects. On one hand, unaware of what OPC/RETs may be employed to synthesize the masks, the designer does not know exactly how to avoid creating wafer patterns that are beyond the capability of the process technology to be used, even with the help of OPC/RETs, which lead to non-manufacturable or low-yield chip designs. On the other hand, uninformed about the intents of the device, circuit, and logic of a design, the fab or process group should not replace, re-route, or otherwise modify the designed wafer patterns in a drastic manner, when trying to fix a “hot-spot” on wafer layout that is difficult to fabricate or completely beyond the process capability. Even being able to approximately produce the designed wafer patterns with the help of OPC/RETs, there are unavoidable deviations of actually obtained wafer patterns from the designed, which lead to uncontrolled variations of RC parameters, and in turn uncontrolled variations of signal timing and integrity, that eventually may result in parametric chip failure.
Typical IC design includes as part of the physical design, steps of physical layout, design rule check (DRC), RC extraction and electric rule check (ERC), timing analysis and signal integrity check, power and thermal analyses etc. (see, for example, M. D. Birnbaum, Essential Electronic Design Automation (EDA), Prentice Hall, 2004). The IC design data passed to the physical layout tools is typically a netlist of devices generated by a prior step, with the devices characterized by electrical parameters. The physical layout step continues the design flow by creating mask patterns that will be used in the manufacturing process to generate intended patterns on a semiconductor (usually silicon) wafer, hereinafter referred collectively as the design intent. The DRC/ERC steps then make sure that there is no violation to a set of design constraints in the intended patterns. The set of design constraints consists of requirements and restrictions on the intended patterns, and/or extracted RC parameters from the intended patterns, as well as circuit timing, signal integrity, and device power consumption, etc. For example, a set of geometric design constraints may require that (1) the linewidth of an intended pattern feature has to be wider than a first limit and narrower than a second limit, (2) the spacing between two intended pattern features has to be more than a third limit, and (3) an edge of an intended pattern feature has to be accurately placed at a desired location within a predetermined tolerance. Among the above exemplary design constraints, the first two types are referred to as feature-size bounds, since they set requirements and restrictions on the sizes of lines or spaces, or equivalently, on the distances between pairs of edges of intended pattern features. The third type is referred to as edge placement bounds, since it dictates where edges have to be located to within a tolerance. For another example, a set of electric design constraints may require that (1) the resistance of a metal or semiconductor structure be within a first range, (2) the capacitance between two metal or semiconductor structures be within a second range. Some design constraints may be requirements from the theory and experiments of device physics, which have to be satisfied in order for the fabricated devices to function properly. Other design constraints may come from theoretical and empirical restrictions imposed by the manufacturing process, which are experiences and experimental results accumulated over time. Such constraints are employed to ensure that the intended patterns lead to functioning devices.
Note that as used herein, the term “design constraints” is intended to be broader than the conventional term “design rules” that refers to geometric design rules, such as feature-size bounds and edge-placement bounds. As used herein, “design constraints” refers to conventional “design rules” as well as other types of constraints, such as electric parameter constraints, signal timing constraints, signal integrity constraints, and chip power consumption constraints, etc.
In the so-called deep-sub-wavelength regime, the features on wafers are so tiny (less than half of the wavelength of the exposure light, which, for example, may be 193 nm or below) and so dense that it is becoming increasingly difficult to create actual patterns on the wafer, referred as wafer patterns, resembling with high fidelity the intended patterns drawn by IC design engineers/tools. It is necessary to distinguish between (1) the intended patterns generated during physical design and (2) the actual patterns created on wafers during the manufacturing process. The former are called intended patterns because they are laid out by IC designers/tools and represent the intended microelectronic features to realize the desired devices and circuits. The latter are called wafer patterns because they are the patterns actually obtained on a processed wafer. Although the wafer patterns may never be exactly the same as the intended patterns, a manufacturing process ideally should be optimized so as to minimize the difference. Conventional DRC tools check the intended patterns against the design constraints. This conventional technique has significant drawbacks, however, due to the inevitable difference between the intended and wafer patterns. Attempts have been made to perform process verification that uses a computer model simulating the manufacturing process, and predict wafer patterns using computer simulations. The predicted wafer patterns are then checked against the design constraints, in an attempt to ascertain whether all predicted wafer patterns fall within the feature-size and edge-placement bounds as well as other constraints. Such simulation-based tools of process verification have been implemented in commercial software products, being called variously as litho rule checking (LRC), silicon versus layout (SiVL) from Synopsys®, optical rule checking (ORC), and OPC verification (OPCverify) (See, for example, see the Calibre MDP product line from Mentor Graphics®.) However, existing products of simulation-based process verification are only capable of modeling a manufacturing process and simulating the wafer patterns under one, usually the best, process condition. For example, the simulations usually assume a process under the best focus of the lithographic imaging system (often referred as the optical stepper) and the ideal level of exposure dosage. Practical manufacturing is always subject to process variations. Defocus, which is deviation of the wafer position from the best focal surface, and fluctuation of exposure dosage are but two sources of process variations among others. Such process variations could degrade the quality of lithographic pattern transfer, resulting in wafer patterns that fall out of the feature-size and edge-placement bounds, which eventually lead to yield loss. PCT Published Application No. WO 2005/098686 entitled “Modeling Resolution Enhancement Process in Integrated Circuit Fabrication” proposes a Wafer Image Modeling and Prediction System that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in IC fabrication. However, in order to characterize more than a single process condition, being proposed is the use of multiple printing models each of which is associated with and derived using a discrete process condition. The generation and use of such multiple printing models involve excessive complexity and cost for test wafer exposures, test data measurements, model calibrations, and applications of models in printing simulations. Furthermore, the validity of such multiple discrete models is limited to strictly the discrete process conditions used for model calibration, or within rather small regions in close proximity to the corresponding discrete process conditions. Thus there is a need for simulation techniques that do not require separate derivation of models for each discrete processing condition.